1. Field of the Invention
The present invention relates to a wiring board for mounting a semiconductor element thereon.
2. Description of the Related Art
A conventional wiring board 40 used for mounting thereon a semiconductor element S′, such as a semiconductor integrated circuit element, is shown in FIG. 4. The wiring board 40 includes an insulting substrate 21 having a plurality of build-up insulating layers 21b respectively laminated on upper and lower surfaces of a core insulating layer 21a, wiring conductors 22 respectively disposed inside the insulating substrates 21 and on upper and lower surfaces thereof, and a solder resist layer 23 adhered onto the outermost insulating layer 21b and the wiring conductors 22.
A mounting part 40A disposed in a middle portion of an upper surface of the wiring board 40 is a square-shaped region for mounting the semiconductor element S′ thereon. A large number of semiconductor element connection pads 24 are arranged in a two-dimensional layout on the mounting part 40A. The semiconductor element connection pads 24 are formed by exposing a part of the wiring conductor 22 adhered to the upper surface of the insulating substrate 21 from openings disposed in the overlying solder resist layer 23. An electrode T′ of the semiconductor element S′ is connected to the semiconductor element connection pads 24 by flip-chip connection.
A lower surface of the wiring board 40 serves as a connection surface with respect to an external electrical circuit board, and a large number of external connection pads 25 are arranged in a two-dimensional layout over an approximately entire region of the connection surface. The external connection pads 25 are formed by exposing a part of the wiring conductor 22 adhered to the lower surface of the insulating substrate 21 from openings disposed in the underlying solder resist layer 23. The external connection pads 25 are connected to a wiring conductor of the external electrical circuit board with, for example, a solder ball interposed therebetween.
A large number of through holes 26 are disposed in the insulating layer 21a. A through conductor 27 is adhered into the through holes 26. The wiring conductors 22 on the upper and lower surfaces of the insulating layer 21a are connected to each other via the through conductor 27.
A large number of via holes 28 are disposed in each of the insulating layers 21b. A through conductor 29 is adhered into the via holes 28. The overlying and underlying wiring conductors 22 are connected to each other via the through conductor 29 and with the insulating layer 21b interposed therebetween.
The wiring conductors 22 including the semiconductor element connection pads 24 and the external connection pads 25 are individually used for signal, grounding, and power supply. Most of the semiconductor element connection pads 24 for signal are disposed along a peripheral portion of the mounting part 40A. Most of the semiconductor element connection pads 24 for grounding and the semiconductor element connection pads 24 for power supply are disposed in a middle portion of the mounting part 40A. Most of the external connection pads 25 for signal are disposed along a peripheral portion of the lower surface of the insulating substrate 21. The external connection pads 25 for grounding and the external connection pads 25 for power supply are disposed in a middle portion and a peripheral portion of the lower surface of the insulating substrate 21.
The semiconductor element connection pads 24 respectively for signal, grounding, and power supply, and the external connection pads 25 respectively for signal, grounding, and power supply are connected to one another via the wiring conductors 22 respectively for signal, grounding, and power supply. The wiring conductor 22 for signal has a band-shaped pattern 30 extending from a region of the surface of the insulating layer 21b laminated on the upper surface of the insulating layer 21a which corresponds to the mounting part 40A, toward a peripheral portion of the insulating plate 21. The band-shaped pattern 30 and the semiconductor element connection pads 24 for signal are connected to each other directly or via the through conductor 29 in the region corresponding to the mounting part 40A. The band-shaped pattern 30 and the external connection pads 25 for signal are connected to each other via the through conductors 27 and 29 in the peripheral portion of the insulating substrate 21.
The wiring conductor 22 for grounding and the wiring conductor 22 for power supply have a solid pattern 31 having a large area disposed oppositely to the wiring conductor 22 for signal. The solid pattern 31 is disposed on the surface of the internal insulating layer 21b that is laminated on the upper surface of the insulating layer 21a. The solid pattern 31 extends from the region corresponding to the mounting part 40A to the peripheral portion of the insulating substrate 21 over a wide range. The solid pattern 31 and the semiconductor element connection pads 24 for grounding or power supply are connected to each other via the through conductor 29 in a region immediately below the mounting part 40A. The solid pattern 31 and the external connection pads 25 for grounding or power supply are connected to each other via the through conductors 27 and 29 in a region of the insulating substrate 21 which extends from a middle portion thereof to a peripheral portion thereof.
FIG. 5 is a plan view showing a main part of the solid pattern 31 for grounding or power supply. In FIG. 5, positions of the external connection pads 25 for grounding or power supply are indicated by a dotted line. An upper left region indicated by an alternate long and two short dashes line is the region corresponding to the mounting part 40A.
The solid pattern 31 has a large number of land openings 32 in the region corresponding to the mounting part 40A. Via lands 33 are respectively disposed in the land openings 32. The solid pattern 31 and the via lands 33 are spaced a predetermined distance. The through conductor 29 of the overlying insulating layer 21b is connected onto the via lands 33. The via lands 33 are respectively connected to the semiconductor element connection pads 24 via the through conductor 29 connected onto the via lands 33. The semiconductor element connection pads 24 to be respectively connected to the via lands 33 are the semiconductor element connection pads 24 for grounding, power supply, or signal which have a different potential from that of the solid pattern 31.
The solid pattern 31 has via connection parts 34 with respect to the overlying conductor layer 22 at positions indicated by a circle of broken line in the region corresponding to the mounting part 40A. The through conductor 29 of the overlying insulating layer 21b is connected onto the via connection parts 34. The solid pattern 31 is connected to the semiconductor element connection pads 24 for grounding or power supply which have the same potential as the solid pattern 31, via the through conductor 29 connected onto the via connection parts 34.
The solid pattern 31 has via connection parts 35 with respect to the underlying conductor layer 22 at positions indicated by a circle of broken line in a region corresponding to a peripheral portion of the wiring board 40. The through conductor 29 of the underlying insulating layer 21b is connected beneath the via connection parts 35. The solid pattern 31 is connected to the external connection pads 25 for grounding or power supply which have the same potential as the solid pattern 31, via the through conductor 29 connected to the via connection parts 35.
The solid pattern 31 includes a large number of gas vent holes 36. The gas vent openings 36 are dispersedly disposed over the entirety of a region not provided with the land opening 32. The gas vent openings 36 are disposed to discharge outgas generated from the insulating layers 21a and 21b to the outside. In the absence of the gas vent openings 36, it is highly possible that swelling and peeling occur between the insulating layer 21a or 21b and the wiring conductor 22 lying thereabove due to the outgas. The occurrence of swelling and peeling may impair a normal function of the wiring board 40. Therefore, the gas vent openings 36 are indispensable for the wiring board 40.
Recently, an operating voltage in the semiconductor element S′ as shown in FIG. 4 has been decreased and a current needed for operation has been increased. In the wiring board 40 having the semiconductor element S′ mounted thereon, a voltage drop (IR Drop) between the semiconductor element connection pads 24 and the external connection pads 25 in the wiring conductor 22 for grounding and the wiring conductor 22 for power supply is preferably as small as possible.
For example, in a wiring board proposed in Japanese Unexamined Patent Publication No. 2011-249734, openings that permit direct adhesion between a solder resist layer and an insulating substrate are disposed around semiconductor element connection pads in a region extending from a solid pattern around a mounting part to the mounting part. The openings thus formed make it possible to decrease a proportion of an area occupied by a wiring conductor layer in the region. This contributes to reducing thermal stress that occurs between the wiring conductor layer and the solder resist layer due to a difference in coefficient of thermal expansion therebetween, thereby increasing an area that permits direct adhesion between the insulating substrate and the solder resist layer. It is therefore concluded that the insulating substrate and the solder resist layer can be strongly adhered to each other.
However, the openings of the wiring board proposed in Japanese Unexamined Patent Publication No. 2011-249734 and the large number of gas vent openings 36 disposed in the solid pattern 31 shown in FIG. 5 act to increase an electrical resistance value of the solid pattern 31. This results in a large voltage drop between the semiconductor element connection pads 24 and the external connection pads 25 in the wiring conductor 22 for grounding and the wiring conductor 22 for power supply. When the semiconductor element S′ having a low operating voltage and a large operating current is mounted on the conventional wiring board 40, it may be difficult to ensure sufficient power supply to the semiconductor element S′, thus failing to ensure normal operation of the semiconductor element S′.